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https://github.com/dolphin-emu/dolphin.git
synced 2026-01-25 16:45:37 +00:00
7dbc623dc0
Doesn't support all the FPSCR flags, just the FPRF ones. Add PPCAnalyzer support to remove unnecessary FPRF calculations. POV-ray benchmark with enableFPRF forced on for an extreme comparison: Before: 1500s After, fmul/fmadd only: 728s After, all float: 753s In real games that use FPRF, like F-Zero GX, FPRF previously cost a few percent of total runtime. Since FPRF is so much faster now, if enableFPRF is set, just do it for every float instruction, not just fmul/fmadd like before. I don't know if this will fix any games, but there's little good reason not to.
263 lines
6.9 KiB
C++
263 lines
6.9 KiB
C++
// Copyright 2013 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#include "Common/BreakPoints.h"
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#include "Common/Common.h"
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#include "Core/Debugger/PPCDebugInterface.h"
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#include "Core/PowerPC/CPUCoreBase.h"
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#include "Core/PowerPC/Gekko.h"
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#include "Core/PowerPC/PPCCache.h"
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class PointerWrap;
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extern CPUCoreBase *cpu_core_base;
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namespace PowerPC
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{
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enum CoreMode
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{
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MODE_INTERPRETER,
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MODE_JIT,
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};
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// This contains the entire state of the emulated PowerPC "Gekko" CPU.
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struct GC_ALIGNED64(PowerPCState)
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{
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u32 gpr[32]; // General purpose registers. r1 = stack pointer.
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// The paired singles are strange : PS0 is stored in the full 64 bits of each FPR
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// but ps calculations are only done in 32-bit precision, and PS1 is only 32 bits.
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// Since we want to use SIMD, SSE2 is the only viable alternative - 2x double.
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u64 ps[32][2];
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u32 pc; // program counter
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u32 npc;
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// Optimized CR implementation. Instead of storing CR in its PowerPC format
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// (4 bit value, SO/EQ/LT/GT), we store instead a 64 bit value for each of
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// the 8 CR register parts. This 64 bit value follows this format:
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// - SO iff. bit 61 is set
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// - EQ iff. lower 32 bits == 0
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// - GT iff. (s64)cr_val > 0
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// - LT iff. bit 62 is set
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//
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// This has the interesting property that sign-extending the result of an
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// operation from 32 to 64 bits results in a 64 bit value that works as a
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// CR value. Checking each part of CR is also fast, as it is equivalent to
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// testing one bit or the low 32 bit part of a register. And CR can still
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// be manipulated bit by bit fairly easily.
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u64 cr_val[8];
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u32 msr; // machine specific register
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u32 fpscr; // floating point flags/status bits
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// Exception management.
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volatile u32 Exceptions;
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// Downcount for determining when we need to do timing
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// This isn't quite the right location for it, but it is here to accelerate the ARM JIT
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// This variable should be inside of the CoreTiming namespace if we wanted to be correct.
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int downcount;
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u32 sr[16]; // Segment registers.
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u32 DebugCount;
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// special purpose registers - controls quantizers, DMA, and lots of other misc extensions.
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// also for power management, but we don't care about that.
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u32 spr[1024];
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u32 dtlb_last;
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u32 dtlb_va[128];
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u32 dtlb_pa[128];
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u32 itlb_last;
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u32 itlb_va[128];
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u32 itlb_pa[128];
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u32 pagetable_base;
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u32 pagetable_hashmask;
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InstructionCache iCache;
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};
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enum CPUState
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{
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CPU_RUNNING = 0,
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CPU_STEPPING = 2,
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CPU_POWERDOWN = 3,
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};
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extern PowerPCState ppcState;
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extern BreakPoints breakpoints;
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extern MemChecks memchecks;
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extern PPCDebugInterface debug_interface;
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void Init(int cpu_core);
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void Shutdown();
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void DoState(PointerWrap &p);
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CoreMode GetMode();
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void SetMode(CoreMode _coreType);
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void SingleStep();
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void CheckExceptions();
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void CheckExternalExceptions();
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void CheckBreakPoints();
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void RunLoop();
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void Start();
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void Pause();
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void Stop();
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CPUState GetState();
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volatile CPUState *GetStatePtr(); // this oddity is here instead of an extern declaration to easily be able to find all direct accesses throughout the code.
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u32 CompactCR();
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void ExpandCR(u32 cr);
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void OnIdle(u32 _uThreadAddr);
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void OnIdleIL();
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void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst);
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// Easy register access macros.
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#define HID0 ((UReg_HID0&)PowerPC::ppcState.spr[SPR_HID0])
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#define HID2 ((UReg_HID2&)PowerPC::ppcState.spr[SPR_HID2])
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#define HID4 ((UReg_HID4&)PowerPC::ppcState.spr[SPR_HID4])
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#define DMAU (*(UReg_DMAU*)&PowerPC::ppcState.spr[SPR_DMAU])
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#define DMAL (*(UReg_DMAL*)&PowerPC::ppcState.spr[SPR_DMAL])
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#define MMCR0 ((UReg_MMCR0&)PowerPC::ppcState.spr[SPR_MMCR0])
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#define MMCR1 ((UReg_MMCR1&)PowerPC::ppcState.spr[SPR_MMCR1])
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#define PC PowerPC::ppcState.pc
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#define NPC PowerPC::ppcState.npc
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#define FPSCR ((UReg_FPSCR&)PowerPC::ppcState.fpscr)
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#define MSR PowerPC::ppcState.msr
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#define GPR(n) PowerPC::ppcState.gpr[n]
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#define rGPR PowerPC::ppcState.gpr
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#define rSPR(i) PowerPC::ppcState.spr[i]
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#define LR PowerPC::ppcState.spr[SPR_LR]
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#define CTR PowerPC::ppcState.spr[SPR_CTR]
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#define rDEC PowerPC::ppcState.spr[SPR_DEC]
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#define SRR0 PowerPC::ppcState.spr[SPR_SRR0]
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#define SRR1 PowerPC::ppcState.spr[SPR_SRR1]
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#define SPRG0 PowerPC::ppcState.spr[SPR_SPRG0]
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#define SPRG1 PowerPC::ppcState.spr[SPR_SPRG1]
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#define SPRG2 PowerPC::ppcState.spr[SPR_SPRG2]
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#define SPRG3 PowerPC::ppcState.spr[SPR_SPRG3]
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#define GQR(x) PowerPC::ppcState.spr[SPR_GQR0+x]
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#define TL PowerPC::ppcState.spr[SPR_TL]
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#define TU PowerPC::ppcState.spr[SPR_TU]
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#define rPS0(i) (*(double*)(&PowerPC::ppcState.ps[i][0]))
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#define rPS1(i) (*(double*)(&PowerPC::ppcState.ps[i][1]))
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#define riPS0(i) (*(u64*)(&PowerPC::ppcState.ps[i][0]))
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#define riPS1(i) (*(u64*)(&PowerPC::ppcState.ps[i][1]))
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} // namespace
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enum CRBits
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{
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CR_SO = 1,
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CR_EQ = 2,
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CR_GT = 4,
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CR_LT = 8,
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CR_SO_BIT = 0,
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CR_EQ_BIT = 1,
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CR_GT_BIT = 2,
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CR_LT_BIT = 3,
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};
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// Convert between PPC and internal representation of CR.
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inline u64 PPCCRToInternal(u8 value)
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{
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u64 cr_val = 0x100000000;
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cr_val |= (u64)!!(value & CR_SO) << 61;
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cr_val |= (u64)!(value & CR_EQ);
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cr_val |= (u64)!(value & CR_GT) << 63;
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cr_val |= (u64)!!(value & CR_LT) << 62;
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return cr_val;
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}
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// convert flags into 64-bit CR values with a lookup table
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extern const u64 m_crTable[16];
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// Warning: these CR operations are fairly slow since they need to convert from
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// PowerPC format (4 bit) to our internal 64 bit format. See the definition of
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// ppcState.cr_val for more explanations.
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inline void SetCRField(int cr_field, int value)
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{
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PowerPC::ppcState.cr_val[cr_field] = m_crTable[value];
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}
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inline u32 GetCRField(int cr_field) {
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u64 cr_val = PowerPC::ppcState.cr_val[cr_field];
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u32 ppc_cr = 0;
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// SO
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ppc_cr |= !!(cr_val & (1ull << 61));
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// EQ
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ppc_cr |= ((cr_val & 0xFFFFFFFF) == 0) << 1;
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// GT
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ppc_cr |= ((s64)cr_val > 0) << 2;
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// LT
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ppc_cr |= !!(cr_val & (1ull << 62)) << 3;
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return ppc_cr;
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}
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inline u32 GetCRBit(int bit) {
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return (GetCRField(bit >> 2) >> (3 - (bit & 3))) & 1;
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}
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inline void SetCRBit(int bit, int value) {
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if (value & 1)
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SetCRField(bit >> 2, GetCRField(bit >> 2) | (0x8 >> (bit & 3)));
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else
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SetCRField(bit >> 2, GetCRField(bit >> 2) & ~(0x8 >> (bit & 3)));
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}
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// SetCR and GetCR are fairly slow. Should be avoided if possible.
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inline void SetCR(u32 new_cr) {
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PowerPC::ExpandCR(new_cr);
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}
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inline u32 GetCR() {
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return PowerPC::CompactCR();
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}
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// SetCarry/GetCarry may speed up soon.
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inline void SetCarry(int ca) {
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((UReg_XER&)PowerPC::ppcState.spr[SPR_XER]).CA = ca;
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}
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inline int GetCarry() {
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return ((UReg_XER&)PowerPC::ppcState.spr[SPR_XER]).CA;
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}
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inline UReg_XER GetXER() {
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return ((UReg_XER&)PowerPC::ppcState.spr[SPR_XER]);
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}
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inline void SetXER(UReg_XER new_xer) {
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((UReg_XER&)PowerPC::ppcState.spr[SPR_XER]) = new_xer;
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}
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inline int GetXER_SO() {
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return ((UReg_XER&)PowerPC::ppcState.spr[SPR_XER]).SO;
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}
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inline void SetXER_SO(int value) {
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((UReg_XER&)PowerPC::ppcState.spr[SPR_XER]).SO = value;
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}
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void UpdateFPRF(double dvalue);
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