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Common: Switch movh/lps to auto SSE/AVX

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TellowKrinkle 2025-08-09 17:45:23 -05:00 committed by TellowKrinkle
parent 94d87a35be
commit a052a43b84
3 changed files with 42 additions and 18 deletions
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20
common/emitter/implement/simd_moremovs.h
View File

@ -14,13 +14,15 @@ namespace x86Emitter
//
struct xImplSimd_MovHL
{
u16 Opcode;
SIMDInstructionInfo info;
void PS(const xRegisterSSE& to, const xIndirectVoid& from) const;
void PS(const xIndirectVoid& to, const xRegisterSSE& from) const;
void PS(const xRegisterSSE& dst, const xIndirectVoid& src) const { PS(dst, dst, src); }
void PS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirectVoid& src2) const;
void PS(const xIndirectVoid& dst, const xRegisterSSE& src) const;
void PD(const xRegisterSSE& to, const xIndirectVoid& from) const;
void PD(const xIndirectVoid& to, const xRegisterSSE& from) const;
void PD(const xRegisterSSE& dst, const xIndirectVoid& src) const { PD(dst, dst, src); }
void PD(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirectVoid& src2) const;
void PD(const xIndirectVoid& dst, const xRegisterSSE& src) const;
};
// --------------------------------------------------------------------------------------
@ -31,10 +33,12 @@ namespace x86Emitter
//
struct xImplSimd_MovHL_RtoR
{
u16 Opcode;
SIMDInstructionInfo info;
void PS(const xRegisterSSE& to, const xRegisterSSE& from) const;
void PD(const xRegisterSSE& to, const xRegisterSSE& from) const;
void PS(const xRegisterSSE& dst, const xRegisterSSE& src) const { PS(dst, dst, src); }
void PD(const xRegisterSSE& dst, const xRegisterSSE& src) const { PD(dst, dst, src); }
void PS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2) const;
void PD(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2) const;
};
// --------------------------------------------------------------------------------------

26
common/emitter/simd.cpp
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@ -628,18 +628,24 @@ namespace x86Emitter
const xImplSimd_PInsert xPINSR;
const SimdImpl_PExtract xPEXTR;
static SIMDInstructionInfo nextop(SIMDInstructionInfo op)
{
op.opcode++;
return op;
}
// =====================================================================================================
// SIMD Move And Blend Instructions
// =====================================================================================================
void xImplSimd_MovHL::PS(const xRegisterSSE& to, const xIndirectVoid& from) const { xOpWrite0F(Opcode, to, from); }
void xImplSimd_MovHL::PS(const xIndirectVoid& to, const xRegisterSSE& from) const { xOpWrite0F(Opcode + 1, from, to); }
void xImplSimd_MovHL::PS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirectVoid& src2) const { EmitSIMD(info, dst, src1, src2); }
void xImplSimd_MovHL::PS(const xIndirectVoid& dst, const xRegisterSSE& src) const { EmitSIMD(nextop(info).mov(), src, src, dst); }
void xImplSimd_MovHL::PD(const xRegisterSSE& to, const xIndirectVoid& from) const { xOpWrite0F(0x66, Opcode, to, from); }
void xImplSimd_MovHL::PD(const xIndirectVoid& to, const xRegisterSSE& from) const { xOpWrite0F(0x66, Opcode + 1, from, to); }
void xImplSimd_MovHL::PD(const xRegisterSSE& dst, const xRegisterSSE& src1, const xIndirectVoid& src2) const { EmitSIMD(info.p66(), dst, src1, src2); }
void xImplSimd_MovHL::PD(const xIndirectVoid& dst, const xRegisterSSE& src) const { EmitSIMD(nextop(info).p66().mov(), src, src, dst); }
void xImplSimd_MovHL_RtoR::PS(const xRegisterSSE& to, const xRegisterSSE& from) const { xOpWrite0F(Opcode, to, from); }
void xImplSimd_MovHL_RtoR::PD(const xRegisterSSE& to, const xRegisterSSE& from) const { xOpWrite0F(0x66, Opcode, to, from); }
void xImplSimd_MovHL_RtoR::PS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2) const { EmitSIMD(info, dst, src1, src2); }
void xImplSimd_MovHL_RtoR::PD(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2) const { EmitSIMD(info.p66(), dst, src1, src2); }
static const u16 MovPS_OpAligned = 0x28; // Aligned [aps] form
static const u16 MovPS_OpUnaligned = 0x10; // unaligned [ups] form
@ -727,11 +733,11 @@ namespace x86Emitter
#endif
const xImplSimd_MovHL xMOVH = {0x16};
const xImplSimd_MovHL xMOVL = {0x12};
const xImplSimd_MovHL xMOVH = {SIMDInstructionInfo(0x16)};
const xImplSimd_MovHL xMOVL = {SIMDInstructionInfo(0x12)};
const xImplSimd_MovHL_RtoR xMOVLH = {0x16};
const xImplSimd_MovHL_RtoR xMOVHL = {0x12};
const xImplSimd_MovHL_RtoR xMOVLH = {SIMDInstructionInfo(0x16)};
const xImplSimd_MovHL_RtoR xMOVHL = {SIMDInstructionInfo(0x12)};
const xImplSimd_PBlend xPBLEND =
{

14
tests/ctest/common/x86emitter/codegen_tests_main.cpp
View File

@ -330,6 +330,13 @@ TEST(CodegenTests, SSETest)
CODEGEN_TEST(xUNPCK.HPS(xmm1, xmm8), "41 0f 15 c8");
CODEGEN_TEST(xUNPCK.HPD(xmm8, xmm2), "66 44 0f 15 c2");
CODEGEN_TEST(xMOVH.PS(ptr[r8], xmm2), "41 0f 17 10");
CODEGEN_TEST(xMOVH.PD(xmm2, ptr[rcx]), "66 0f 16 11");
CODEGEN_TEST(xMOVL.PS(xmm8, ptr[rax]), "44 0f 12 00");
CODEGEN_TEST(xMOVL.PD(ptr[r8 + r9], xmm9), "66 47 0f 13 0c 08");
CODEGEN_TEST(xMOVHL.PS(xmm4, xmm9), "41 0f 12 e1");
CODEGEN_TEST(xMOVLH.PS(xmm2, xmm1), "0f 16 d1");
CODEGEN_TEST(xMOVAPS(xmm0, xmm1), "0f 28 c1");
CODEGEN_TEST(xMOVAPS(xmm8, xmm9), "45 0f 28 c1");
CODEGEN_TEST(xMOVUPS(xmm8, ptr128[r8+r9]), "47 0f 10 04 08");
@ -531,6 +538,13 @@ TEST(CodegenTests, AVXTest)
CODEGEN_TEST(xUNPCK.HPS(xmm1, xmm8), "c4 c1 70 15 c8");
CODEGEN_TEST(xUNPCK.HPD(xmm8, xmm2), "c5 39 15 c2");
CODEGEN_TEST(xMOVH.PS(ptr[r8], xmm2), "c4 c1 78 17 10");
CODEGEN_TEST(xMOVH.PD(xmm2, ptr[rcx]), "c5 e9 16 11");
CODEGEN_TEST(xMOVL.PS(xmm8, ptr[rax]), "c5 38 12 00");
CODEGEN_TEST(xMOVL.PD(ptr[r8 + r9], xmm9), "c4 01 79 13 0c 08");
CODEGEN_TEST(xMOVHL.PS(xmm4, xmm9), "c4 c1 58 12 e1");
CODEGEN_TEST(xMOVLH.PS(xmm2, xmm1), "c5 e8 16 d1");
CODEGEN_TEST(xVMOVAPS(xmm0, xmm1), "c5 f8 28 c1");
CODEGEN_TEST(xVMOVAPS(xmm0, ptr32[rdi]), "c5 f8 28 07");
CODEGEN_TEST(xVMOVAPS(ptr32[rdi], xmm0), "c5 f8 29 07");