mirror of
https://github.com/PCSX2/pcsx2.git
synced 2025-12-16 04:08:48 +00:00
Common: Remove dedicated AVX instructions
The main instructions *are* AVX instructions now
This commit is contained in:
TellowKrinkle
TellowKrinkle
parent
d9ff9d7aa1
commit
cc5f594384
@ -85,7 +85,6 @@ target_sources(common PRIVATE
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if(_M_X86)
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target_sources(common PRIVATE
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emitter/avx.cpp
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emitter/bmi.cpp
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emitter/fpu.cpp
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emitter/groups.cpp
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@ -80,9 +80,6 @@
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<ClCompile Include="Windows\WinThreads.cpp" />
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<ClCompile Include="HostSys.cpp" />
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<ClCompile Include="Semaphore.cpp" />
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<ClCompile Include="emitter\avx.cpp">
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<ExcludedFromBuild Condition="'$(Platform)'=='ARM64'">true</ExcludedFromBuild>
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</ClCompile>
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<ClCompile Include="emitter\bmi.cpp">
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<ExcludedFromBuild Condition="'$(Platform)'=='ARM64'">true</ExcludedFromBuild>
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</ClCompile>
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@ -1,172 +0,0 @@
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// SPDX-FileCopyrightText: 2002-2025 PCSX2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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#include "common/emitter/internal.h"
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// warning: suggest braces around initialization of subobject [-Wmissing-braces]
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#ifdef __clang__
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wmissing-braces"
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#endif
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namespace x86Emitter
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{
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const xImplAVX_Move xVMOVAPS = {0x00, 0x28, 0x29};
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const xImplAVX_Move xVMOVUPS = {0x00, 0x10, 0x11};
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const xImplAVX_ArithFloat xVADD = {
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{0x00, 0x58}, // VADDPS
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{0x66, 0x58}, // VADDPD
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{0xF3, 0x58}, // VADDSS
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{0xF2, 0x58}, // VADDSD
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};
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const xImplAVX_ArithFloat xVSUB = {
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{0x00, 0x5C}, // VSUBPS
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{0x66, 0x5C}, // VSUBPD
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{0xF3, 0x5C}, // VSUBSS
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{0xF2, 0x5C}, // VSUBSD
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};
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const xImplAVX_ArithFloat xVMUL = {
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{0x00, 0x59}, // VMULPS
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{0x66, 0x59}, // VMULPD
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{0xF3, 0x59}, // VMULSS
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{0xF2, 0x59}, // VMULSD
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};
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const xImplAVX_ArithFloat xVDIV = {
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{0x00, 0x5E}, // VDIVPS
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{0x66, 0x5E}, // VDIVPD
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{0xF3, 0x5E}, // VDIVSS
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{0xF2, 0x5E}, // VDIVSD
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};
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const xImplAVX_CmpFloat xVCMP = {
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{SSE2_Equal},
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{SSE2_Less},
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{SSE2_LessOrEqual},
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{SSE2_Unordered},
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{SSE2_NotEqual},
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{SSE2_NotLess},
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{SSE2_NotLessOrEqual},
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{SSE2_Ordered},
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};
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const xImplAVX_ThreeArgYMM xVPAND = {0x66, 0xDB};
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const xImplAVX_ThreeArgYMM xVPANDN = {0x66, 0xDF};
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const xImplAVX_ThreeArgYMM xVPOR = {0x66, 0xEB};
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const xImplAVX_ThreeArgYMM xVPXOR = {0x66, 0xEF};
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const xImplAVX_CmpInt xVPCMP = {
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{0x66, 0x74}, // VPCMPEQB
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{0x66, 0x75}, // VPCMPEQW
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{0x66, 0x76}, // VPCMPEQD
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{0x66, 0x64}, // VPCMPGTB
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{0x66, 0x65}, // VPCMPGTW
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{0x66, 0x66}, // VPCMPGTD
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};
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void xVPMOVMSKB(const xRegister32& to, const xRegisterSSE& from)
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{
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xOpWriteC5(0x66, 0xd7, to, xRegister32(), from);
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}
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void xVMOVMSKPS(const xRegister32& to, const xRegisterSSE& from)
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{
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xOpWriteC5(0x00, 0x50, to, xRegister32(), from);
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}
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void xVMOVMSKPD(const xRegister32& to, const xRegisterSSE& from)
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{
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xOpWriteC5(0x66, 0x50, to, xRegister32(), from);
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}
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void xVZEROUPPER()
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{
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// rather than dealing with nonexistant operands..
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xWrite8(0xc5);
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xWrite8(0xf8);
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xWrite8(0x77);
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}
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void xImplAVX_Move::operator()(const xRegisterSSE& to, const xRegisterSSE& from) const
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{
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if (to != from)
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xOpWriteC5(Prefix, LoadOpcode, to, xRegisterSSE(), from);
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}
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void xImplAVX_Move::operator()(const xRegisterSSE& to, const xIndirectVoid& from) const
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{
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xOpWriteC5(Prefix, LoadOpcode, to, xRegisterSSE(), from);
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}
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void xImplAVX_Move::operator()(const xIndirectVoid& to, const xRegisterSSE& from) const
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{
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xOpWriteC5(Prefix, StoreOpcode, from, xRegisterSSE(), to);
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}
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void xImplAVX_ThreeArg::operator()(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const
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{
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pxAssert(!to.IsWideSIMD() && !from1.IsWideSIMD() && !from2.IsWideSIMD());
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xOpWriteC5(Prefix, Opcode, to, from1, from2);
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}
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void xImplAVX_ThreeArg::operator()(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const
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{
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pxAssert(!to.IsWideSIMD() && !from1.IsWideSIMD());
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xOpWriteC5(Prefix, Opcode, to, from1, from2);
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}
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void xImplAVX_ThreeArgYMM::operator()(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const
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{
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xOpWriteC5(Prefix, Opcode, to, from1, from2);
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}
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void xImplAVX_ThreeArgYMM::operator()(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const
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{
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xOpWriteC5(Prefix, Opcode, to, from1, from2);
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}
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void xImplAVX_CmpFloatHelper::PS(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const
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{
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xOpWriteC5(0x00, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::PS(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const
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{
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xOpWriteC5(0x00, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::PD(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const
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{
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xOpWriteC5(0x66, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::PD(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const
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{
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xOpWriteC5(0x66, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::SS(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const
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{
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xOpWriteC5(0xF3, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::SS(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const
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{
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xOpWriteC5(0xF3, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::SD(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const
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{
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xOpWriteC5(0xF2, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::SD(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const
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{
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xOpWriteC5(0xF2, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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} // namespace x86Emitter
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@ -621,22 +621,6 @@ namespace x86Emitter
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// ------------------------------------------------------------------------
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extern const xImplAVX_Move xVMOVAPS;
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extern const xImplAVX_Move xVMOVUPS;
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extern const xImplAVX_ArithFloat xVADD;
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extern const xImplAVX_ArithFloat xVSUB;
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extern const xImplAVX_ArithFloat xVMUL;
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extern const xImplAVX_ArithFloat xVDIV;
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extern const xImplAVX_CmpFloat xVCMP;
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extern const xImplAVX_ThreeArgYMM xVPAND;
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extern const xImplAVX_ThreeArgYMM xVPANDN;
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extern const xImplAVX_ThreeArgYMM xVPOR;
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extern const xImplAVX_ThreeArgYMM xVPXOR;
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extern const xImplAVX_CmpInt xVPCMP;
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extern void xVPMOVMSKB(const xRegister32& to, const xRegisterSSE& from);
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extern void xVMOVMSKPS(const xRegister32& to, const xRegisterSSE& from);
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extern void xVMOVMSKPD(const xRegister32& to, const xRegisterSSE& from);
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extern void xVZEROUPPER();
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} // namespace x86Emitter
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@ -910,4 +910,12 @@ namespace x86Emitter
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{
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xOpWrite0F(0, 0xae, 1, src);
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}
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void xVZEROUPPER()
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{
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// rather than dealing with nonexistant operands..
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xWrite8(0xc5);
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xWrite8(0xf8);
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xWrite8(0x77);
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}
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} // namespace x86Emitter
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@ -209,13 +209,13 @@ static void mVUGenerateCopyPipelineState(mV)
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if (g_cpu.vectorISA >= ProcessorFeatures::VectorISA::AVX)
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{
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xVMOVAPS(ymm0, ptr[rax]);
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xVMOVAPS(ymm1, ptr[rax + 32u]);
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xVMOVAPS(ymm2, ptr[rax + 64u]);
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xMOVAPS(ymm0, ptr[rax]);
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xMOVAPS(ymm1, ptr[rax + 32u]);
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xMOVAPS(ymm2, ptr[rax + 64u]);
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xVMOVUPS(ptr[reinterpret_cast<u8*>(&mVU.prog.lpState)], ymm0);
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xVMOVUPS(ptr[reinterpret_cast<u8*>(&mVU.prog.lpState) + 32u], ymm1);
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xVMOVUPS(ptr[reinterpret_cast<u8*>(&mVU.prog.lpState) + 64u], ymm2);
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xMOVUPS(ptr[reinterpret_cast<u8*>(&mVU.prog.lpState)], ymm0);
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xMOVUPS(ptr[reinterpret_cast<u8*>(&mVU.prog.lpState) + 32u], ymm1);
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xMOVUPS(ptr[reinterpret_cast<u8*>(&mVU.prog.lpState) + 64u], ymm2);
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xVZEROUPPER();
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}
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@ -285,19 +285,19 @@ static void mVUGenerateCompareState(mV)
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else
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{
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// We have to use unaligned loads here, because the blocks are only 16 byte aligned.
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xVMOVUPS(ymm0, ptr[arg1reg]);
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xVPCMP.EQD(ymm0, ymm0, ptr[arg2reg]);
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xVPMOVMSKB(eax, ymm0);
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xMOVUPS(ymm0, ptr[arg1reg]);
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xPCMP.EQD(ymm0, ymm0, ptr[arg2reg]);
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xPMOVMSKB(eax, ymm0);
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xXOR(eax, 0xffffffff);
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xForwardJNZ8 exitPoint;
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xVMOVUPS(ymm0, ptr[arg1reg + 0x20]);
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xVMOVUPS(ymm1, ptr[arg1reg + 0x40]);
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xVPCMP.EQD(ymm0, ymm0, ptr[arg2reg + 0x20]);
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xVPCMP.EQD(ymm1, ymm1, ptr[arg2reg + 0x40]);
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xVPAND(ymm0, ymm0, ymm1);
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xMOVUPS(ymm0, ptr[arg1reg + 0x20]);
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xMOVUPS(ymm1, ptr[arg1reg + 0x40]);
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xPCMP.EQD(ymm0, ymm0, ptr[arg2reg + 0x20]);
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xPCMP.EQD(ymm1, ymm1, ptr[arg2reg + 0x40]);
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xPAND(ymm0, ymm0, ymm1);
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xVPMOVMSKB(eax, ymm0);
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xPMOVMSKB(eax, ymm0);
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xNOT(eax);
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exitPoint.SetTarget();
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@ -747,96 +747,48 @@ TEST(CodegenTests, AVXTest)
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CODEGEN_TEST(xPMOVMSKB(eax, xmm2), "c5 f9 d7 c2");
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CODEGEN_TEST(xPALIGNR(xmm4, xmm8, 1), "c4 c3 59 0f e0 01");
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CODEGEN_TEST(xMASKMOV(xmm2, xmm9), "c4 c1 79 f7 d1");
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CODEGEN_TEST(xVMOVAPS(xmm0, xmm1), "c5 f8 28 c1");
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CODEGEN_TEST(xVMOVAPS(xmm0, ptr32[rdi]), "c5 f8 28 07");
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CODEGEN_TEST(xVMOVAPS(ptr32[rdi], xmm0), "c5 f8 29 07");
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CODEGEN_TEST(xVMOVUPS(xmm0, ptr32[rdi]), "c5 f8 10 07");
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CODEGEN_TEST(xVMOVUPS(ptr32[rdi], xmm0), "c5 f8 11 07");
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CODEGEN_TEST(xVADD.PS(xmm0, xmm1, xmm2), "c5 f0 58 c2");
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CODEGEN_TEST(xVADD.PD(xmm0, xmm1, xmm2), "c5 f1 58 c2");
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CODEGEN_TEST(xVADD.SS(xmm0, xmm1, xmm2), "c5 f2 58 c2");
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CODEGEN_TEST(xVADD.SD(xmm0, xmm1, xmm2), "c5 f3 58 c2");
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CODEGEN_TEST(xVSUB.PS(xmm0, xmm1, xmm2), "c5 f0 5c c2");
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CODEGEN_TEST(xVSUB.PD(xmm0, xmm1, xmm2), "c5 f1 5c c2");
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CODEGEN_TEST(xVSUB.SS(xmm0, xmm1, xmm2), "c5 f2 5c c2");
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CODEGEN_TEST(xVSUB.SD(xmm0, xmm1, xmm2), "c5 f3 5c c2");
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CODEGEN_TEST(xVMUL.PS(xmm0, xmm1, xmm2), "c5 f0 59 c2");
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CODEGEN_TEST(xVMUL.PD(xmm0, xmm1, xmm2), "c5 f1 59 c2");
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CODEGEN_TEST(xVMUL.SS(xmm0, xmm1, xmm2), "c5 f2 59 c2");
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CODEGEN_TEST(xVMUL.SD(xmm0, xmm1, xmm2), "c5 f3 59 c2");
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CODEGEN_TEST(xVDIV.PS(xmm0, xmm1, xmm2), "c5 f0 5e c2");
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CODEGEN_TEST(xVDIV.PD(xmm0, xmm1, xmm2), "c5 f1 5e c2");
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CODEGEN_TEST(xVDIV.SS(xmm0, xmm1, xmm2), "c5 f2 5e c2");
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CODEGEN_TEST(xVDIV.SD(xmm0, xmm1, xmm2), "c5 f3 5e c2");
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// Don't need to test all variants, since they just change the condition immediate.
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CODEGEN_TEST(xVCMP.EQ.PS(xmm0, xmm1, xmm2), "c5 f0 c2 c2 00");
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CODEGEN_TEST(xVCMP.EQ.PD(xmm0, xmm1, xmm2), "c5 f1 c2 c2 00");
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CODEGEN_TEST(xVCMP.EQ.SS(xmm0, xmm1, xmm2), "c5 f2 c2 c2 00");
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CODEGEN_TEST(xVCMP.EQ.SD(xmm0, xmm1, xmm2), "c5 f3 c2 c2 00");
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CODEGEN_TEST(xVCMP.LE.PS(xmm0, xmm1, xmm2), "c5 f0 c2 c2 02");
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CODEGEN_TEST(xVCMP.LE.PD(xmm0, xmm1, xmm2), "c5 f1 c2 c2 02");
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CODEGEN_TEST(xVCMP.LE.SS(xmm0, xmm1, xmm2), "c5 f2 c2 c2 02");
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CODEGEN_TEST(xVCMP.LE.SD(xmm0, xmm1, xmm2), "c5 f3 c2 c2 02");
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CODEGEN_TEST(xVPCMP.EQB(xmm0, xmm1, xmm2), "c5 f1 74 c2");
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CODEGEN_TEST(xVPCMP.EQW(xmm0, xmm1, xmm2), "c5 f1 75 c2");
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CODEGEN_TEST(xVPCMP.EQD(xmm0, xmm1, xmm2), "c5 f1 76 c2");
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CODEGEN_TEST(xVPCMP.GTB(xmm0, xmm1, xmm2), "c5 f1 64 c2");
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CODEGEN_TEST(xVPCMP.GTW(xmm0, xmm1, xmm2), "c5 f1 65 c2");
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CODEGEN_TEST(xVPCMP.GTD(xmm0, xmm1, xmm2), "c5 f1 66 c2");
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CODEGEN_TEST(xVPAND(xmm0, xmm1, xmm2), "c5 f1 db c2");
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CODEGEN_TEST(xVPANDN(xmm0, xmm1, xmm2), "c5 f1 df c2");
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CODEGEN_TEST(xVPOR(xmm0, xmm1, xmm2), "c5 f1 eb c2");
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CODEGEN_TEST(xVPXOR(xmm0, xmm1, xmm2), "c5 f1 ef c2");
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CODEGEN_TEST(xVMOVMSKPS(eax, xmm1), "c5 f8 50 c1");
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CODEGEN_TEST(xVMOVMSKPD(eax, xmm1), "c5 f9 50 c1");
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}
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TEST(CodegenTests, AVX256Test)
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{
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x86Emitter::use_avx = true;
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CODEGEN_TEST(xVMOVAPS(ymm0, ymm1), "c5 fc 28 c1");
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CODEGEN_TEST(xVMOVAPS(ymm0, ptr32[rdi]), "c5 fc 28 07");
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CODEGEN_TEST(xVMOVAPS(ptr32[rdi], ymm0), "c5 fc 29 07");
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CODEGEN_TEST(xVMOVUPS(ymm0, ptr32[rdi]), "c5 fc 10 07");
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CODEGEN_TEST(xVMOVUPS(ptr32[rdi], ymm0), "c5 fc 11 07");
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CODEGEN_TEST(xMOVAPS(ymm0, ymm1), "c5 fc 28 c1");
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CODEGEN_TEST(xMOVAPS(ymm0, ptr32[rdi]), "c5 fc 28 07");
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CODEGEN_TEST(xMOVAPS(ptr32[rdi], ymm0), "c5 fc 29 07");
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CODEGEN_TEST(xMOVUPS(ymm0, ptr32[rdi]), "c5 fc 10 07");
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CODEGEN_TEST(xMOVUPS(ptr32[rdi], ymm0), "c5 fc 11 07");
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CODEGEN_TEST(xVZEROUPPER(), "c5 f8 77");
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CODEGEN_TEST(xVADD.PS(ymm0, ymm1, ymm2), "c5 f4 58 c2");
|
||||
CODEGEN_TEST(xVADD.PD(ymm0, ymm1, ymm2), "c5 f5 58 c2");
|
||||
CODEGEN_TEST(xVSUB.PS(ymm0, ymm1, ymm2), "c5 f4 5c c2");
|
||||
CODEGEN_TEST(xVSUB.PD(ymm0, ymm1, ymm2), "c5 f5 5c c2");
|
||||
CODEGEN_TEST(xVMUL.PS(ymm0, ymm1, ymm2), "c5 f4 59 c2");
|
||||
CODEGEN_TEST(xVMUL.PD(ymm0, ymm1, ymm2), "c5 f5 59 c2");
|
||||
CODEGEN_TEST(xVDIV.PS(ymm0, ymm1, ymm2), "c5 f4 5e c2");
|
||||
CODEGEN_TEST(xVDIV.PD(ymm0, ymm1, ymm2), "c5 f5 5e c2");
|
||||
CODEGEN_TEST(xADD.PS(ymm0, ymm1, ymm2), "c5 f4 58 c2");
|
||||
CODEGEN_TEST(xADD.PD(ymm0, ymm1, ymm2), "c5 f5 58 c2");
|
||||
CODEGEN_TEST(xSUB.PS(ymm0, ymm1, ymm2), "c5 f4 5c c2");
|
||||
CODEGEN_TEST(xSUB.PD(ymm0, ymm1, ymm2), "c5 f5 5c c2");
|
||||
CODEGEN_TEST(xMUL.PS(ymm0, ymm1, ymm2), "c5 f4 59 c2");
|
||||
CODEGEN_TEST(xMUL.PD(ymm0, ymm1, ymm2), "c5 f5 59 c2");
|
||||
CODEGEN_TEST(xDIV.PS(ymm0, ymm1, ymm2), "c5 f4 5e c2");
|
||||
CODEGEN_TEST(xDIV.PD(ymm0, ymm1, ymm2), "c5 f5 5e c2");
|
||||
|
||||
CODEGEN_TEST(xVCMP.EQ.PS(ymm0, ymm1, ymm2), "c5 f4 c2 c2 00");
|
||||
CODEGEN_TEST(xVCMP.EQ.PD(ymm0, ymm1, ymm2), "c5 f5 c2 c2 00");
|
||||
CODEGEN_TEST(xVCMP.LE.PS(ymm0, ymm1, ymm2), "c5 f4 c2 c2 02");
|
||||
CODEGEN_TEST(xVCMP.LE.PD(ymm0, ymm1, ymm2), "c5 f5 c2 c2 02");
|
||||
CODEGEN_TEST(xCMPEQ.PS(ymm0, ymm1, ymm2), "c5 f4 c2 c2 00");
|
||||
CODEGEN_TEST(xCMPEQ.PD(ymm0, ymm1, ymm2), "c5 f5 c2 c2 00");
|
||||
CODEGEN_TEST(xCMPLE.PS(ymm0, ymm1, ymm2), "c5 f4 c2 c2 02");
|
||||
CODEGEN_TEST(xCMPLE.PD(ymm0, ymm1, ymm2), "c5 f5 c2 c2 02");
|
||||
|
||||
CODEGEN_TEST(xVPCMP.EQB(ymm0, ymm1, ymm2), "c5 f5 74 c2");
|
||||
CODEGEN_TEST(xVPCMP.EQW(ymm0, ymm1, ymm2), "c5 f5 75 c2");
|
||||
CODEGEN_TEST(xVPCMP.EQD(ymm0, ymm1, ymm2), "c5 f5 76 c2");
|
||||
CODEGEN_TEST(xVPCMP.GTB(ymm0, ymm1, ymm2), "c5 f5 64 c2");
|
||||
CODEGEN_TEST(xVPCMP.GTW(ymm0, ymm1, ymm2), "c5 f5 65 c2");
|
||||
CODEGEN_TEST(xVPCMP.GTD(ymm0, ymm1, ymm2), "c5 f5 66 c2");
|
||||
CODEGEN_TEST(xPCMP.EQB(ymm0, ymm1, ymm2), "c5 f5 74 c2");
|
||||
CODEGEN_TEST(xPCMP.EQW(ymm0, ymm1, ymm2), "c5 f5 75 c2");
|
||||
CODEGEN_TEST(xPCMP.EQD(ymm0, ymm1, ymm2), "c5 f5 76 c2");
|
||||
CODEGEN_TEST(xPCMP.GTB(ymm0, ymm1, ymm2), "c5 f5 64 c2");
|
||||
CODEGEN_TEST(xPCMP.GTW(ymm0, ymm1, ymm2), "c5 f5 65 c2");
|
||||
CODEGEN_TEST(xPCMP.GTD(ymm0, ymm1, ymm2), "c5 f5 66 c2");
|
||||
|
||||
CODEGEN_TEST(xVPAND(ymm0, ymm1, ymm2), "c5 f5 db c2");
|
||||
CODEGEN_TEST(xVPANDN(ymm0, ymm1, ymm2), "c5 f5 df c2");
|
||||
CODEGEN_TEST(xVPOR(ymm0, ymm1, ymm2), "c5 f5 eb c2");
|
||||
CODEGEN_TEST(xVPXOR(ymm0, ymm1, ymm2), "c5 f5 ef c2");
|
||||
CODEGEN_TEST(xPAND(ymm0, ymm1, ymm2), "c5 f5 db c2");
|
||||
CODEGEN_TEST(xPANDN(ymm0, ymm1, ymm2), "c5 f5 df c2");
|
||||
CODEGEN_TEST(xPOR(ymm0, ymm1, ymm2), "c5 f5 eb c2");
|
||||
CODEGEN_TEST(xPXOR(ymm0, ymm1, ymm2), "c5 f5 ef c2");
|
||||
|
||||
CODEGEN_TEST(xVMOVMSKPS(eax, ymm1), "c5 fc 50 c1");
|
||||
CODEGEN_TEST(xVMOVMSKPD(eax, ymm1), "c5 fd 50 c1");
|
||||
CODEGEN_TEST(xMOVMSKPS(eax, ymm1), "c5 fc 50 c1");
|
||||
CODEGEN_TEST(xMOVMSKPD(eax, ymm1), "c5 fd 50 c1");
|
||||
}
|
||||
|
||||
TEST(CodegenTests, Extended8BitTest)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user