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rsx/fp: Re-implement ROP output resolve
This commit is contained in:
kd-11
kd-11
parent
f2913e4692
commit
316e01995b
@ -525,7 +525,6 @@ target_sources(rpcs3_emu PRIVATE
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RSX/Program/CgBinaryFragmentProgram.cpp
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RSX/Program/CgBinaryVertexProgram.cpp
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RSX/Program/FragmentProgramDecompiler.cpp
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RSX/Program/FragmentProgramRegister.cpp
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RSX/Program/GLSLCommon.cpp
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RSX/Program/ProgramStateCache.cpp
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RSX/Program/program_util.cpp
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@ -14,6 +14,8 @@ namespace rsx
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{
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namespace fragment_program
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{
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using namespace rsx::assembler;
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static const std::string reg_table[] =
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{
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"wpos",
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@ -22,6 +24,28 @@ namespace rsx
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"tc0", "tc1", "tc2", "tc3", "tc4", "tc5", "tc6", "tc7", "tc8", "tc9",
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"ssa"
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};
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static const std::vector<RegisterRef> s_fp32_output_set =
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{
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{.reg {.id = 0, .f16 = false }, .mask = 0xf },
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{.reg {.id = 2, .f16 = false }, .mask = 0xf },
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{.reg {.id = 3, .f16 = false }, .mask = 0xf },
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{.reg {.id = 4, .f16 = false }, .mask = 0xf },
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};
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static const std::vector<RegisterRef> s_fp16_output_set =
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{
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{.reg {.id = 0, .f16 = true }, .mask = 0xf },
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{.reg {.id = 4, .f16 = true }, .mask = 0xf },
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{.reg {.id = 6, .f16 = true }, .mask = 0xf },
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{.reg {.id = 8, .f16 = true }, .mask = 0xf },
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};
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static const RegisterRef s_z_export_reg =
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{
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.reg {.id = 1, .f16 = false },
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.mask = (1u << 2)
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};
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}
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}
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@ -37,6 +61,26 @@ enum VectorLane : u8
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W = 3,
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};
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std::vector<RegisterRef> get_fragment_program_output_set(u32 ctrl, u32 mrt_count)
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{
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std::vector<RegisterRef> result;
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if (mrt_count > 0)
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{
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result = (ctrl & CELL_GCM_SHADER_CONTROL_32_BITS_EXPORTS)
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? s_fp32_output_set
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: s_fp16_output_set;
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result.resize(mrt_count);
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}
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if (ctrl & CELL_GCM_SHADER_CONTROL_DEPTH_EXPORT)
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{
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result.push_back(s_z_export_reg);
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}
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return result;
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}
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FragmentProgramDecompiler::FragmentProgramDecompiler(const RSXFragmentProgram &prog, u32& size)
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: m_size(size)
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, m_prog(prog)
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@ -157,8 +201,6 @@ void FragmentProgramDecompiler::SetDst(std::string code, u32 flags)
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}
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const u32 reg_index = dst.fp16 ? (dst.dest_reg >> 1) : dst.dest_reg;
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ensure(reg_index < temp_registers.size());
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if (dst.opcode == RSX_FP_OPCODE_MOV &&
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src0.reg_type == RSX_FP_REGISTER_TYPE_TEMP &&
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src0.tmp_reg_index == reg_index)
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@ -171,8 +213,6 @@ void FragmentProgramDecompiler::SetDst(std::string code, u32 flags)
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return;
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}
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}
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temp_registers[reg_index].tag(dst.dest_reg, !!dst.fp16, dst.mask_x, dst.mask_y, dst.mask_z, dst.mask_w);
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}
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void FragmentProgramDecompiler::AddFlowOp(const std::string& code)
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@ -528,26 +568,7 @@ template<typename T> std::string FragmentProgramDecompiler::GetSRC(T src)
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switch (src.reg_type)
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{
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case RSX_FP_REGISTER_TYPE_TEMP:
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if (!src.fp16)
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{
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if (dst.opcode == RSX_FP_OPCODE_UP16 ||
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dst.opcode == RSX_FP_OPCODE_UP2 ||
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dst.opcode == RSX_FP_OPCODE_UP4 ||
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dst.opcode == RSX_FP_OPCODE_UPB ||
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dst.opcode == RSX_FP_OPCODE_UPG)
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{
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auto ® = temp_registers[src.tmp_reg_index];
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if (reg.requires_gather(src.swizzle_x))
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{
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properties.has_gather_op = true;
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AddReg(src.tmp_reg_index, src.fp16);
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ret = getFloatTypeName(4) + reg.gather_r();
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break;
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}
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}
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}
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else if (precision_modifier == RSX_FP_PRECISION_HALF)
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if (src.fp16 && precision_modifier == RSX_FP_PRECISION_HALF)
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{
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// clamp16() is not a cheap operation when emulated; avoid at all costs
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precision_modifier = RSX_FP_PRECISION_REAL;
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@ -778,17 +799,6 @@ std::string FragmentProgramDecompiler::BuildCode()
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{
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// Hw tests show that the depth export register is default-initialized to 0 and not wpos.z!!
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m_parr.AddParam(PF_PARAM_NONE, getFloatTypeName(4), "r1", init_value);
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auto& r1 = temp_registers[1];
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if (r1.requires_gather(VectorLane::Z))
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{
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// r1.zw was not written to
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properties.has_gather_op = true;
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main_epilogue << " r1.z = " << float4_type << r1.gather_r() << ".z;\n";
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// Emit debug warning. Useful to diagnose regressions, but should be removed in future.
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rsx_log.warning("ROP reads from shader depth without writing to it. Final value will be gathered.");
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}
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}
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// Add the color output registers. They are statically written to and have guaranteed initialization (except r1.z which == wpos.z)
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@ -816,33 +826,6 @@ std::string FragmentProgramDecompiler::BuildCode()
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continue;
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}
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const auto block_index = ouput_register_indices[n];
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auto& r = temp_registers[block_index];
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if (fp16_out)
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{
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// Check if we need a split/extract op
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if (r.requires_split(0))
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{
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main_epilogue << " " << reg_name << " = " << float4_type << r.split_h0() << ";\n";
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// Emit debug warning. Useful to diagnose regressions, but should be removed in future.
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rsx_log.warning("ROP reads from %s without writing to it. Final value will be extracted from the 32-bit register.", reg_name);
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}
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continue;
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}
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if (!r.requires_gather128())
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{
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// Nothing to do
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continue;
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}
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// We need to gather the data from existing registers
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main_epilogue << " " << reg_name << " = " << float4_type << r.gather_r() << ";\n";
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properties.has_gather_op = true;
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// Emit debug warning. Useful to diagnose regressions, but should be removed in future.
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rsx_log.warning("ROP reads from %s without writing to it. Final value will be gathered.", reg_name);
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}
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@ -1030,28 +1013,6 @@ std::string FragmentProgramDecompiler::BuildCode()
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OS << Format(divsq_func);
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}
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// Declare register gather/merge if needed
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if (properties.has_gather_op)
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{
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std::string float2 = getFloatTypeName(2);
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OS << float4 << " gather(" << float4 << " _h0, " << float4 << " _h1)\n";
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OS << "{\n";
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OS << " float x = uintBitsToFloat(packHalf2x16(_h0.xy));\n";
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OS << " float y = uintBitsToFloat(packHalf2x16(_h0.zw));\n";
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OS << " float z = uintBitsToFloat(packHalf2x16(_h1.xy));\n";
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OS << " float w = uintBitsToFloat(packHalf2x16(_h1.zw));\n";
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OS << " return " << float4 << "(x, y, z, w);\n";
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OS << "}\n\n";
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OS << float2 << " gather(" << float4 << " _h)\n";
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OS << "{\n";
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OS << " float x = uintBitsToFloat(packHalf2x16(_h.xy));\n";
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OS << " float y = uintBitsToFloat(packHalf2x16(_h.zw));\n";
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OS << " return " << float2 << "(x, y);\n";
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OS << "}\n\n";
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}
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if (properties.has_dynamic_register_load)
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{
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OS <<
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@ -1303,8 +1264,28 @@ std::string FragmentProgramDecompiler::Decompile()
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{
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auto graph = deconstruct_fragment_program(m_prog);
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if (g_cfg.video.shader_precision != gpu_preset_level::low)
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if (!graph.blocks.empty())
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{
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// The RSX CFG is missing the output block. We inject a fake tail block that ingests the ROP outputs.
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BasicBlock* rop_block = nullptr;
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BasicBlock* tail_block = &graph.blocks.back();
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if (tail_block->instructions.size() == 0)
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{
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// Merge block. Use this directly
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rop_block = tail_block;
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}
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else
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{
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graph.blocks.push_back({});
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rop_block = &graph.blocks.back();
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tail_block->insert_succ(rop_block);
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rop_block->insert_pred(tail_block);
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}
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const auto rop_inputs = get_fragment_program_output_set(m_prog.ctrl, m_prog.mrt_buffers_count);
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rop_block->input_list.insert(rop_block->input_list.end(), rop_inputs.begin(), rop_inputs.end());
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FP::RegisterAnnotationPass annotation_pass{ m_prog };
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FP::RegisterDependencyPass dependency_pass{};
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@ -1376,6 +1357,9 @@ std::string FragmentProgramDecompiler::Decompile()
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case EdgeType::ENDLOOP:
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// Pure merge block?
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break;
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case EdgeType::NONE:
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ensure(block.instructions.empty());
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break;
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default:
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fmt::throw_exception("Unhandled edge type %d", static_cast<int>(pred.type));
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break;
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@ -1,6 +1,5 @@
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#pragma once
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#include "ShaderParam.h"
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#include "FragmentProgramRegister.h"
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#include "RSXFragmentProgram.h"
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#include "Assembler/CFG.h"
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@ -53,8 +52,6 @@ class FragmentProgramDecompiler
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int m_code_level;
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std::unordered_map<u32, u32> m_constant_offsets;
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std::array<rsx::MixedPrecisionRegister, 64> temp_registers;
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std::string GetMask() const;
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void SetDst(std::string code, u32 flags = 0);
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@ -175,7 +172,6 @@ public:
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// Decoded properties (out)
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bool has_lit_op = false;
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bool has_gather_op = false;
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bool has_no_output = false;
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bool has_discard_op = false;
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bool has_tex_op = false;
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@ -1,196 +0,0 @@
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#include "stdafx.h"
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#include "FragmentProgramRegister.h"
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namespace rsx
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{
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MixedPrecisionRegister::MixedPrecisionRegister()
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{
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std::fill(content_mask.begin(), content_mask.end(), data_type_bits::undefined);
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}
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void MixedPrecisionRegister::tag_h0(bool x, bool y, bool z, bool w)
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{
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if (x) content_mask[0] = data_type_bits::f16;
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if (y) content_mask[1] = data_type_bits::f16;
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if (z) content_mask[2] = data_type_bits::f16;
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if (w) content_mask[3] = data_type_bits::f16;
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}
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void MixedPrecisionRegister::tag_h1(bool x, bool y, bool z, bool w)
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{
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if (x) content_mask[4] = data_type_bits::f16;
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if (y) content_mask[5] = data_type_bits::f16;
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if (z) content_mask[6] = data_type_bits::f16;
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if (w) content_mask[7] = data_type_bits::f16;
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}
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void MixedPrecisionRegister::tag_r(bool x, bool y, bool z, bool w)
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{
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if (x) content_mask[0] = content_mask[1] = data_type_bits::f32;
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if (y) content_mask[2] = content_mask[3] = data_type_bits::f32;
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if (z) content_mask[4] = content_mask[5] = data_type_bits::f32;
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if (w) content_mask[6] = content_mask[7] = data_type_bits::f32;
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}
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void MixedPrecisionRegister::tag(u32 index, bool is_fp16, bool x, bool y, bool z, bool w)
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{
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if (file_index == umax)
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{
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// First-time use. Initialize...
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const u32 real_index = is_fp16 ? (index >> 1) : index;
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file_index = real_index;
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}
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if (is_fp16)
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{
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ensure((index / 2) == file_index);
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if (index & 1)
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{
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tag_h1(x, y, z, w);
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return;
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}
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tag_h0(x, y, z, w);
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return;
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}
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tag_r(x, y, z, w);
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}
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std::string MixedPrecisionRegister::gather_r() const
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{
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const auto half_index = file_index << 1;
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const std::string reg = "r" + std::to_string(file_index);
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const std::string gather_half_regs[] = {
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"gather(h" + std::to_string(half_index) + ")",
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"gather(h" + std::to_string(half_index + 1) + ")"
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};
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std::string outputs[4];
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for (int ch = 0; ch < 4; ++ch)
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{
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// FIXME: This approach ignores mixed register bits. Not ideal!!!!
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const auto channel0 = content_mask[ch * 2];
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const auto is_fp16_ch = channel0 == content_mask[ch * 2 + 1] && channel0 == data_type_bits::f16;
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outputs[ch] = is_fp16_ch ? gather_half_regs[ch / 2] : reg;
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}
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// Grouping. Only replace relevant bits...
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if (outputs[0] == outputs[1]) outputs[0] = "";
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if (outputs[2] == outputs[3]) outputs[2] = "";
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// Assemble
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bool group = false;
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std::string result = "";
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constexpr std::string_view swz_mask = "xyzw";
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for (int ch = 0; ch < 4; ++ch)
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{
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if (outputs[ch].empty())
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{
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group = true;
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continue;
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}
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if (!result.empty())
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{
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result += ", ";
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}
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if (group)
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{
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ensure(ch > 0);
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group = false;
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if (outputs[ch] == reg)
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{
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result += reg + "." + swz_mask[ch - 1] + swz_mask[ch];
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continue;
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}
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result += outputs[ch];
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continue;
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}
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const int subch = outputs[ch] == reg ? ch : (ch % 2); // Avoid .xyxy.z and other such ugly swizzles
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result += outputs[ch] + "." + swz_mask[subch];
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}
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// Optimize dual-gather (128-bit gather) to use special function
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const std::string double_gather = gather_half_regs[0] + ", " + gather_half_regs[1];
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if (result == double_gather)
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{
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result = "gather(h" + std::to_string(half_index) + ", h" + std::to_string(half_index + 1) + ")";
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}
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return "(" + result + ")";
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}
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std::string MixedPrecisionRegister::fetch_halfreg(u32 word_index) const
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{
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// Reads half-word 0 (H16x4) from a full real (R32x4) register
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constexpr std::string_view swz_mask = "xyzw";
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const std::string reg = "r" + std::to_string(file_index);
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const std::string hreg = "h" + std::to_string(file_index * 2 + word_index);
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const std::string word0_bits = "floatBitsToUint(" + reg + "." + swz_mask[word_index * 2] + ")";
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const std::string word1_bits = "floatBitsToUint(" + reg + "." + swz_mask[word_index * 2 + 1] + ")";
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const std::string words[] = {
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"unpackHalf2x16(" + word0_bits + ")",
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"unpackHalf2x16(" + word1_bits + ")"
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};
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// Assemble
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std::string outputs[4];
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ensure(word_index <= 1);
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const int word_offset = word_index * 4;
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for (int ch = 0; ch < 4; ++ch)
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{
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outputs[ch] = content_mask[ch + word_offset] == data_type_bits::f32
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? words[ch / 2]
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: hreg;
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}
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// Grouping. Only replace relevant bits...
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if (outputs[0] == outputs[1]) outputs[0] = "";
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if (outputs[2] == outputs[3]) outputs[2] = "";
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// Assemble
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bool group = false;
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std::string result = "";
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for (int ch = 0; ch < 4; ++ch)
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{
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if (outputs[ch].empty())
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{
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group = true;
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continue;
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}
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if (!result.empty())
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{
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result += ", ";
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}
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if (group)
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{
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ensure(ch > 0);
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group = false;
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result += outputs[ch];
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if (outputs[ch] == hreg)
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{
|
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result += std::string(".") + swz_mask[ch - 1] + swz_mask[ch];
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
||||
const int subch = outputs[ch] == hreg ? ch : (ch % 2); // Avoid .xyxy.z and other such ugly swizzles
|
||||
result += outputs[ch] + "." + swz_mask[subch];
|
||||
}
|
||||
|
||||
return "(" + result + ")";
|
||||
}
|
||||
}
|
||||
@ -1,111 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
#include <util/types.hpp>
|
||||
|
||||
namespace rsx
|
||||
{
|
||||
class MixedPrecisionRegister
|
||||
{
|
||||
enum data_type_bits
|
||||
{
|
||||
undefined = 0,
|
||||
f16 = 1,
|
||||
f32 = 2
|
||||
};
|
||||
|
||||
std::array<data_type_bits, 8> content_mask; // Content details for each half-word
|
||||
u32 file_index = umax;
|
||||
|
||||
void tag_h0(bool x, bool y, bool z, bool w);
|
||||
|
||||
void tag_h1(bool x, bool y, bool z, bool w);
|
||||
|
||||
void tag_r(bool x, bool y, bool z, bool w);
|
||||
|
||||
std::string fetch_halfreg(u32 word_index) const;
|
||||
|
||||
public:
|
||||
MixedPrecisionRegister();
|
||||
|
||||
void tag(u32 index, bool is_fp16, bool x, bool y, bool z, bool w);
|
||||
|
||||
std::string gather_r() const;
|
||||
|
||||
std::string split_h0() const
|
||||
{
|
||||
return fetch_halfreg(0);
|
||||
}
|
||||
|
||||
std::string split_h1() const
|
||||
{
|
||||
return fetch_halfreg(1);
|
||||
}
|
||||
|
||||
// Getters
|
||||
|
||||
// Return true if all values are unwritten to (undefined)
|
||||
bool floating() const
|
||||
{
|
||||
return file_index == umax;
|
||||
}
|
||||
|
||||
// Return true if the first half register is all undefined
|
||||
bool floating_h0() const
|
||||
{
|
||||
return content_mask[0] == content_mask[1] &&
|
||||
content_mask[1] == content_mask[2] &&
|
||||
content_mask[2] == content_mask[3] &&
|
||||
content_mask[3] == data_type_bits::undefined;
|
||||
}
|
||||
|
||||
// Return true if the second half register is all undefined
|
||||
bool floating_h1() const
|
||||
{
|
||||
return content_mask[4] == content_mask[5] &&
|
||||
content_mask[5] == content_mask[6] &&
|
||||
content_mask[6] == content_mask[7] &&
|
||||
content_mask[7] == data_type_bits::undefined;
|
||||
}
|
||||
|
||||
// Return true if any of the half-words are 16-bit
|
||||
bool requires_gather(u8 channel) const
|
||||
{
|
||||
// Data fetched from the single precision register requires merging of the two half registers
|
||||
const auto channel_offset = channel * 2;
|
||||
ensure(channel_offset <= 6);
|
||||
|
||||
return (content_mask[channel_offset] == data_type_bits::f16 || content_mask[channel_offset + 1] == data_type_bits::f16);
|
||||
}
|
||||
|
||||
// Return true if the entire 128-bit register is filled with 2xfp16x4 data words
|
||||
bool requires_gather128() const
|
||||
{
|
||||
// Full 128-bit check
|
||||
for (const auto& ch : content_mask)
|
||||
{
|
||||
if (ch == data_type_bits::f16)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// Return true if the half-register is polluted with fp32 data
|
||||
bool requires_split(u32 word_index) const
|
||||
{
|
||||
const u32 content_offset = word_index * 4;
|
||||
for (u32 i = 0; i < 4; ++i)
|
||||
{
|
||||
if (content_mask[content_offset + i] == data_type_bits::f32)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
@ -161,7 +161,6 @@
|
||||
<ClCompile Include="Emu\RSX\Program\Assembler\FPToCFG.cpp" />
|
||||
<ClCompile Include="Emu\RSX\Program\Assembler\Passes\FP\RegisterAnnotationPass.cpp" />
|
||||
<ClCompile Include="Emu\RSX\Program\Assembler\Passes\FP\RegisterDependencyPass.cpp" />
|
||||
<ClCompile Include="Emu\RSX\Program\FragmentProgramRegister.cpp" />
|
||||
<ClCompile Include="Emu\RSX\Program\ProgramStateCache.cpp" />
|
||||
<ClCompile Include="Emu\RSX\Program\program_util.cpp" />
|
||||
<ClCompile Include="Emu\RSX\Program\SPIRVCommon.cpp" />
|
||||
@ -710,7 +709,6 @@
|
||||
<ClInclude Include="Emu\RSX\Program\Assembler\IR.h" />
|
||||
<ClInclude Include="Emu\RSX\Program\Assembler\Passes\FP\RegisterAnnotationPass.h" />
|
||||
<ClInclude Include="Emu\RSX\Program\Assembler\Passes\FP\RegisterDependencyPass.h" />
|
||||
<ClInclude Include="Emu\RSX\Program\FragmentProgramRegister.h" />
|
||||
<ClInclude Include="Emu\RSX\Program\GLSLTypes.h" />
|
||||
<ClInclude Include="Emu\RSX\Program\ProgramStateCache.h" />
|
||||
<ClInclude Include="Emu\RSX\Program\program_util.h" />
|
||||
|
||||
@ -1360,9 +1360,6 @@
|
||||
<ClCompile Include="Emu\Cell\ErrorCodes.cpp">
|
||||
<Filter>Emu\Cell</Filter>
|
||||
</ClCompile>
|
||||
<ClCompile Include="Emu\RSX\Program\FragmentProgramRegister.cpp">
|
||||
<Filter>Emu\GPU\RSX\Program</Filter>
|
||||
</ClCompile>
|
||||
<ClCompile Include="util\emu_utils.cpp">
|
||||
<Filter>Utilities</Filter>
|
||||
</ClCompile>
|
||||
@ -2764,9 +2761,6 @@
|
||||
<ClInclude Include="Emu\Audio\audio_utils.h">
|
||||
<Filter>Emu\Audio</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="Emu\RSX\Program\FragmentProgramRegister.h">
|
||||
<Filter>Emu\GPU\RSX\Program</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="util\video_source.h">
|
||||
<Filter>Utilities</Filter>
|
||||
</ClInclude>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user