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* Initial implementation * Fix for crash caused by stale stages data; cosmetics applied * Someone mentioned the assert * Async blob writer * Fix for memory leak * Remain stuff * Async changed to `packaged_task`
758 lines
35 KiB
C++
758 lines
35 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "common/assert.h"
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#include "shader_recompiler/info.h"
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#include "shader_recompiler/ir/attribute.h"
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#include "shader_recompiler/ir/breadth_first_search.h"
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#include "shader_recompiler/ir/ir_emitter.h"
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#include "shader_recompiler/ir/opcodes.h"
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#include "shader_recompiler/ir/operand_helper.h"
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#include "shader_recompiler/ir/passes/ir_passes.h"
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#include "shader_recompiler/ir/pattern_matching.h"
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#include "shader_recompiler/ir/program.h"
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#include "shader_recompiler/runtime_info.h"
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namespace Shader::Optimization {
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/**
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* Tessellation shaders pass outputs to the next shader using LDS.
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* The Hull shader stage receives input control points stored in LDS.
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*
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* These passes attempt to resolve LDS accesses to attribute accesses and correctly
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* write to the tessellation factor tables.
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*
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* The LDS layout is:
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* - TCS inputs for patch 0
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* - TCS inputs for patch 1
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* - TCS inputs for patch 2
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* - ...
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* - TCS outputs for patch 0
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* - TCS outputs for patch 1
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* - TCS outputs for patch 2
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* - ...
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* - PatchConst TCS outputs for patch 0
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* - PatchConst TCS outputs for patch 1
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* - PatchConst TCS outputs for patch 2
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*
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*
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* If the Hull stage does not write any new control points the driver will
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* optimize LDS layout so input and output control point spaces overlap.
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* (Passthrough)
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*
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* The gnm driver requires a V# holding special constants to be bound
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* for reads by the shader.
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* The Hull and Domain shaders read values from this buffer which
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* contain size and offset information required to address input, output,
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* or PatchConst attributes within the current patch.
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* See the TessellationDataConstantBuffer struct to see the layout of this V#.
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*
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* Tessellation factors are stored to a special tessellation factor V# that is automatically bound
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* by the driver. This is the input to the fixed function tessellator that actually subdivides the
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* domain. We translate these to writes to SPIR-V builtins for tessellation factors in the Hull
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* shader.
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* The offset into the tess factor buffer determines which factor the shader is writing.
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* Additionally, most hull shaders seem to redundantly write tess factors to PatchConst
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* attributes, even if dead in the domain shader. We just treat these as generic PatchConst writes.
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*
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* LDS reads in the Hull shader can be from input control points, and in the the Domain shader can
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* be hs output control points (output from the perspective of the Hull shader) and patchconst
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* values.
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* LDS stores in the Hull shader can either be output control point writes or per-patch
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* (PatchConst) data writes. The Domain shader exports attributes using EXP instructions, unless its
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* followed by the geometry stage (but we havent seen this yet), so nothing special there.
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* The address calculations can vary significantly and can't be easily pattern matched. We are at
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* the mercy of instruction selection the ps4 compiler wanted to use.
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* Generally though, they could look something like this:
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* Input control point:
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* addr = PatchIdInVgt * input_cp_stride * #input_cp_per_patch + index * input_cp_stride
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* + attr# * 16 + component
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* Output control point:
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* addr = #patches * input_cp_stride * #input_cp_per_patch
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* + PatchIdInVgt * output_patch_stride + InvocationID * output_cp_stride
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+ attr# * 16 + component
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* Per patch output:
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* addr = #patches * input_cp_stride * #cp_per_input_patch
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* + #patches * output_patch_stride
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* + PatchIdInVgt * per_patch_output_stride + attr# * 16 + component
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*
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* output_patch_stride and output_cp_stride are usually compile time constants in the gcn
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*
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* Hull shaders can also read output control points corresponding to other threads.
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* In HLSL style, this should only be possible in the Patch Constant function.
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* TODO we may need to insert additional barriers if sync is free/more permissive
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* on AMD LDS HW
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* They should also be able to read output PatchConst values,
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* although not sure if this happens in practice.
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*
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* To determine which type of attribute (input, output, patchconst) we the check the users of
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* TessConstants V# reads to deduce which type of attribute a given load/store to LDS
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* is touching.
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*
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* In the Hull shader, both the PatchId within the VGT group (PatchIdInVgt) and the output control
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* point id (InvocationId) are packed in VGPR1 by the driver like
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* V1 = InvocationId << 8 | PatchIdInVgt
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* The shader typically uses V_BFE_(U|S)32 to extract them. We use the starting bit_pos to determine
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* which is which.
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*
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* This pass does not attempt to deduce the exact attribute referenced in a LDS load/store.
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* Instead, it feeds the address in the LDS load/store to the get/set Insts we use for TCS in/out's,
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* TES in's, and PatchConst in/out's.
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*
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* TCS/TES Input attributes:
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* We define input attributes using an array in the shader roughly like this:
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* // equivalent GLSL in TCS
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* layout (location = 0) in vec4 in_attrs[][NUM_INPUT_ATTRIBUTES];
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*
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* Here the NUM_INPUT_ATTRIBUTES is derived from the ls_stride member of the TessConstants V#.
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* We take ALIGN_UP(ls_stride, 16) / 16 to get the number of vec4 attributes.
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* For TES, NUM_INPUT_ATTRIBUTES is ALIGN_UP(hs_cp_stride, 16) / 16.
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* The first (outer) dimension is unsized but corresponds to the number of vertices in the hs input
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* patch (for Hull) or the hs output patch (for Domain).
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*
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* For input reads in TCS or TES, we emit SPIR-V like:
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* float value = in_attrs[addr / ls_stride][(addr % ls_stride) >> 4][(addr % ls_stride) >> 2];
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*
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* For output writes, we assume the control point index is InvocationId, since high level languages
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* impose that restriction (although maybe it's technically possible on hardware). So SPIR-V looks
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* like this:
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* layout (location = 0) in vec4 in_attrs[][NUM_OUTPUT_ATTRIBUTES];
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* out_attrs[InvocationId][(addr % hs_cp_stride) >> 4][(addr % hs_cp_stride) >> 2] = value;
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*
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* NUM_OUTPUT_ATTRIBUTES is derived by ALIGN_UP(hs_cp_stride, 16) / 16, so it matches
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* NUM_INPUT_ATTRIBUTES of the TES.
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*
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* Another challenge is the fact that the GCN shader needs to address attributes from LDS as a whole
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* which contains the attributes from many patches. On the other hand, higher level shading
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* languages restrict attribute access to the patch of the current thread, which is naturally a
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* restriction in SPIR-V also.
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* The addresses the ps4 compiler generates for loads/stores and the fact that LDS holds many
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* patches' attributes are just implementation details of the ps4 driver/compiler. To deal with
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* this, we can replace certain TessConstant V# reads with 0, which only contribute to the base
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* address of the current patch's attributes in LDS and not the indexes within the local patch.
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*
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* (A perfect implementation might need emulation of the VGTs in mesh/compute, loading/storing
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* attributes to buffers and not caring about whether they are hs input, hs output, or patchconst
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* attributes)
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*
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*/
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namespace {
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using namespace Shader::Optimiation::PatternMatching;
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static void InitTessConstants(IR::ScalarReg sharp_ptr_base, s32 sharp_dword_offset,
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Shader::Info& info, Shader::RuntimeInfo& runtime_info,
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TessellationDataConstantBuffer& tess_constants) {
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info.tess_consts_ptr_base = sharp_ptr_base;
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info.tess_consts_dword_offset = sharp_dword_offset;
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info.ReadTessConstantBuffer(tess_constants);
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if (info.l_stage == LogicalStage::TessellationControl) {
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runtime_info.hs_info.InitFromTessConstants(tess_constants);
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} else {
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runtime_info.vs_info.InitFromTessConstants(tess_constants);
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}
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return;
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}
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struct TessSharpLocation {
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IR::ScalarReg ptr_base;
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u32 dword_off;
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};
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std::optional<TessSharpLocation> FindTessConstantSharp(IR::Inst* read_const_buffer) {
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IR::Value sharp_ptr_base;
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IR::Value sharp_dword_offset;
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IR::Value rv = IR::Value{read_const_buffer};
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IR::Value handle = read_const_buffer->Arg(0);
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if (M_COMPOSITECONSTRUCTU32X4(M_GETUSERDATA(MatchImm(sharp_dword_offset)), MatchIgnore(),
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MatchIgnore(), MatchIgnore())
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.Match(handle)) {
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return TessSharpLocation{.ptr_base = IR::ScalarReg::Max,
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.dword_off = static_cast<u32>(sharp_dword_offset.ScalarReg())};
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} else if (M_COMPOSITECONSTRUCTU32X4(
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M_READCONST(M_COMPOSITECONSTRUCTU32X2(M_GETUSERDATA(MatchImm(sharp_ptr_base)),
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MatchIgnore()),
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MatchImm(sharp_dword_offset)),
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MatchIgnore(), MatchIgnore(), MatchIgnore())
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.Match(handle)) {
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return TessSharpLocation{.ptr_base = sharp_ptr_base.ScalarReg(),
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.dword_off = sharp_dword_offset.U32()};
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}
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return {};
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}
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// Walker that helps deduce what type of attribute a DS instruction is reading
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// or writing, which could be an input control point, output control point,
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// or per-patch constant (PatchConst).
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// For certain ReadConstBuffer instructions using the tess constants V#,, we visit the users
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// recursively and increment a counter on the Load/WriteShared users.
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// Namely NumPatch (from m_hsNumPatch), HsOutputBase (m_hsOutputBase),
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// and PatchConstBase (m_patchConstBase).
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// In addr calculations, the term NumPatch * ls_stride * #input_cp_in_patch
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// is used as an addend to skip the region for input control points, and similarly
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// NumPatch * hs_cp_stride * #output_cp_in_patch is used to skip the region
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// for output control points.
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//
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// TODO: this will break if AMD compiler used distributive property like
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// TcsNumPatches * (ls_stride * #input_cp_in_patch + hs_cp_stride * #output_cp_in_patch)
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class TessConstantUseWalker {
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public:
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void MarkTessAttributeUsers(IR::Inst* read_const_buffer, TessConstantAttribute attr) {
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u32 inc;
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switch (attr) {
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case TessConstantAttribute::HsNumPatch:
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case TessConstantAttribute::HsOutputBase:
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inc = 1;
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break;
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case TessConstantAttribute::PatchConstBase:
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inc = 2;
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break;
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default:
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UNREACHABLE();
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}
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for (IR::Use use : read_const_buffer->Uses()) {
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MarkTessAttributeUsersHelper(use, inc);
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}
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++seq_num;
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}
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private:
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void MarkTessAttributeUsersHelper(IR::Use use, u32 inc) {
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IR::Inst* inst = use.user;
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switch (use.user->GetOpcode()) {
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case IR::Opcode::LoadSharedU32:
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case IR::Opcode::LoadSharedU64:
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case IR::Opcode::WriteSharedU32:
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case IR::Opcode::WriteSharedU64: {
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u32 counter = inst->Flags<u32>();
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inst->SetFlags<u32>(counter + inc);
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// Stop here
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return;
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}
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case IR::Opcode::Phi: {
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struct PhiCounter {
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u16 seq_num;
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u16 unique_edge;
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};
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PhiCounter count = inst->Flags<PhiCounter>();
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ASSERT_MSG(count.seq_num == 0 || count.unique_edge == use.operand);
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// the point of seq_num is to tell us if we've already traversed this
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// phi on the current walk. Alternatively we could keep a set of phi's
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// seen on the current walk. This is to handle phi cycles
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if (count.seq_num == 0) {
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// First time we've encountered this phi
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count.seq_num = seq_num;
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// Mark the phi as having been traversed originally through this edge
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count.unique_edge = use.operand;
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} else if (count.seq_num < seq_num) {
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count.seq_num = seq_num;
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// For now, assume we are visiting this phi via the same edge
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// as on other walks. If not, some dataflow analysis might be necessary
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ASSERT(count.unique_edge == use.operand);
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} else {
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// count.seq_num == seq_num
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// there's a cycle, and we've already been here on this walk
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return;
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}
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inst->SetFlags<PhiCounter>(count);
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break;
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}
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default:
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break;
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}
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for (IR::Use use : inst->Uses()) {
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MarkTessAttributeUsersHelper(use, inc);
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}
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}
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u32 seq_num{1u};
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};
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enum class AttributeRegion : u32 { InputCP, OutputCP, PatchConst };
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static AttributeRegion GetAttributeRegionKind(IR::Inst* ring_access, const Shader::Info& info,
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const Shader::RuntimeInfo& runtime_info) {
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u32 count = ring_access->Flags<u32>();
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if (count == 0) {
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return AttributeRegion::InputCP;
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} else if (info.l_stage == LogicalStage::TessellationControl &&
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runtime_info.hs_info.IsPassthrough()) {
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ASSERT(count <= 1);
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return AttributeRegion::PatchConst;
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} else {
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ASSERT(count <= 2);
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return AttributeRegion(count);
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}
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}
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static bool IsDivisibleByStride(IR::Value term, u32 stride) {
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IR::Value a, b;
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if (MatchU32(stride).Match(term)) {
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return true;
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} else if (M_BITFIELDUEXTRACT(MatchValue(a), MatchU32(0), MatchU32(24)).Match(term) ||
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M_BITFIELDSEXTRACT(MatchValue(a), MatchU32(0), MatchU32(24)).Match(term)) {
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return IsDivisibleByStride(a, stride);
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} else if (M_IMUL32(MatchValue(a), MatchValue(b)).Match(term)) {
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return IsDivisibleByStride(a, stride) || IsDivisibleByStride(b, stride);
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}
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return false;
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}
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// Return true if we can eliminate any addends
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static bool TryOptimizeAddendInModulo(IR::Value addend, u32 stride, std::vector<IR::U32>& addends) {
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IR::Value a, b;
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if (M_IADD32(MatchValue(a), MatchValue(b)).Match(addend)) {
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bool ret = false;
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ret = TryOptimizeAddendInModulo(a, stride, addends);
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ret |= TryOptimizeAddendInModulo(b, stride, addends);
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return ret;
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} else if (!IsDivisibleByStride(addend, stride)) {
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addends.push_back(IR::U32{addend});
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return false;
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} else {
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return true;
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}
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}
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// In calculation (a + b + ...) % stride
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// Use this fact
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// (a + b) mod N = (a mod N + b mod N) mod N
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// If any addend is divisible by stride, then we can replace it with 0 in the attribute
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// or component index calculation
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static IR::U32 TryOptimizeAddressModulo(IR::U32 addr, u32 stride, IR::IREmitter& ir) {
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std::vector<IR::U32> addends;
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if (TryOptimizeAddendInModulo(addr, stride, addends)) {
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addr = ir.Imm32(0);
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for (auto& addend : addends) {
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addr = ir.IAdd(addr, addend);
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}
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}
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return addr;
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}
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// TODO: can optimize div in control point index similarly to mod
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// Read a TCS input (InputCP region) or TES input (OutputCP region)
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static IR::F32 ReadTessControlPointAttribute(IR::U32 addr, const u32 stride, IR::IREmitter& ir,
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u32 off_dw, bool is_output_read_in_tcs) {
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if (off_dw > 0) {
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addr = ir.IAdd(addr, ir.Imm32(off_dw));
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}
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const IR::U32 control_point_index = ir.IDiv(addr, ir.Imm32(stride));
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const IR::U32 opt_addr = TryOptimizeAddressModulo(addr, stride, ir);
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const IR::U32 offset = ir.IMod(opt_addr, ir.Imm32(stride));
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const IR::U32 attr_index = ir.ShiftRightLogical(offset, ir.Imm32(4u));
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const IR::U32 comp_index =
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ir.ShiftRightLogical(ir.BitwiseAnd(offset, ir.Imm32(0xFU)), ir.Imm32(2u));
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if (is_output_read_in_tcs) {
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return ir.ReadTcsGenericOuputAttribute(control_point_index, attr_index, comp_index);
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} else {
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return ir.GetTessGenericAttribute(control_point_index, attr_index, comp_index);
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}
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}
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} // namespace
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void HullShaderTransform(IR::Program& program, const RuntimeInfo& runtime_info) {
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const Info& info = program.info;
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for (IR::Block* block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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const auto opcode = inst.GetOpcode();
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switch (opcode) {
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case IR::Opcode::StoreBufferU32:
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case IR::Opcode::StoreBufferU32x2:
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case IR::Opcode::StoreBufferU32x3:
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case IR::Opcode::StoreBufferU32x4: {
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IR::Value soffset = IR::GetBufferSOffsetArg(&inst);
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if (!M_GETATTRIBUTEU32(MatchAttribute(IR::Attribute::TessFactorsBufferBase),
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MatchIgnore())
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.Match(soffset)) {
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break;
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}
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const auto info = inst.Flags<IR::BufferInstInfo>();
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IR::IREmitter ir{*block, IR::Block::InstructionList::s_iterator_to(inst)};
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IR::Value voffset;
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bool success =
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M_COMPOSITECONSTRUCTU32X3(MatchU32(0), MatchImm(voffset), MatchIgnore())
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.Match(inst.Arg(IR::StoreBufferArgs::Address));
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ASSERT_MSG(success, "unhandled pattern in tess factor store");
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const u32 gcn_factor_idx = (info.inst_offset.Value() + voffset.U32()) >> 2;
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const IR::Value data = inst.Arg(IR::StoreBufferArgs::Data);
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const u32 num_dwords = u32(opcode) - u32(IR::Opcode::StoreBufferU32) + 1;
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const auto GetValue = [&](IR::Value data) -> IR::F32 {
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if (auto* inst = data.TryInstRecursive();
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inst && inst->GetOpcode() == IR::Opcode::BitCastU32F32) {
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return IR::F32{inst->Arg(0)};
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}
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return ir.BitCast<IR::F32, IR::U32>(IR::U32{data});
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};
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auto get_factor_attr = [&](u32 gcn_factor_idx) -> IR::Patch {
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// The hull outputs tess factors in different formats depending on the shader.
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// For triangle domains, it seems to pack the entries into 4 consecutive floats,
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// with the 3 edge factors followed by the 1 interior factor.
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// For quads, it does 4 edge factors then 2 interior.
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// There is a tess factor stride member of the GNMX hull constants struct in
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// a hull program shader binary archive, but this doesn't seem to be
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// communicated to the driver.
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// The layout seems to be implied by the type of the abstract domain.
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switch (runtime_info.hs_info.tess_type) {
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case AmdGpu::TessellationType::Isoline:
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ASSERT(gcn_factor_idx < 2);
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|
return IR::PatchFactor(gcn_factor_idx);
|
|
case AmdGpu::TessellationType::Triangle:
|
|
ASSERT(gcn_factor_idx < 4);
|
|
if (gcn_factor_idx == 3) {
|
|
return IR::Patch::TessellationLodInteriorU;
|
|
}
|
|
return IR::PatchFactor(gcn_factor_idx);
|
|
case AmdGpu::TessellationType::Quad:
|
|
ASSERT(gcn_factor_idx < 6);
|
|
return IR::PatchFactor(gcn_factor_idx);
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
};
|
|
|
|
inst.Invalidate();
|
|
if (num_dwords == 1) {
|
|
ir.SetPatch(get_factor_attr(gcn_factor_idx), GetValue(data));
|
|
break;
|
|
}
|
|
auto* inst = data.TryInstRecursive();
|
|
ASSERT(inst && (inst->GetOpcode() == IR::Opcode::CompositeConstructU32x2 ||
|
|
inst->GetOpcode() == IR::Opcode::CompositeConstructU32x3 ||
|
|
inst->GetOpcode() == IR::Opcode::CompositeConstructU32x4));
|
|
for (s32 i = 0; i < num_dwords; i++) {
|
|
ir.SetPatch(get_factor_attr(gcn_factor_idx + i), GetValue(inst->Arg(i)));
|
|
}
|
|
break;
|
|
}
|
|
|
|
case IR::Opcode::WriteSharedU32:
|
|
case IR::Opcode::WriteSharedU64: {
|
|
IR::IREmitter ir{*block, IR::Block::InstructionList::s_iterator_to(inst)};
|
|
const u32 num_dwords = opcode == IR::Opcode::WriteSharedU32 ? 1 : 2;
|
|
const IR::U32 addr{inst.Arg(0)};
|
|
const IR::Value data = num_dwords == 2
|
|
? ir.UnpackUint2x32(IR::U64{inst.Arg(1).Resolve()})
|
|
: inst.Arg(1).Resolve();
|
|
|
|
const auto SetOutput = [&](IR::U32 addr, IR::U32 value, AttributeRegion output_kind,
|
|
u32 off_dw) {
|
|
const IR::F32 data_component = ir.BitCast<IR::F32, IR::U32>(value);
|
|
|
|
if (output_kind == AttributeRegion::OutputCP) {
|
|
if (off_dw > 0) {
|
|
addr = ir.IAdd(addr, ir.Imm32(off_dw));
|
|
}
|
|
const u32 stride = runtime_info.hs_info.hs_output_cp_stride;
|
|
// Invocation ID array index is implicit, handled by SPIRV backend
|
|
const IR::U32 opt_addr = TryOptimizeAddressModulo(addr, stride, ir);
|
|
const IR::U32 offset = ir.IMod(opt_addr, ir.Imm32(stride));
|
|
const IR::U32 attr_index = ir.ShiftRightLogical(offset, ir.Imm32(4u));
|
|
const IR::U32 comp_index = ir.ShiftRightLogical(
|
|
ir.BitwiseAnd(offset, ir.Imm32(0xFU)), ir.Imm32(2u));
|
|
ir.SetTcsGenericAttribute(data_component, attr_index, comp_index);
|
|
} else {
|
|
ASSERT(output_kind == AttributeRegion::PatchConst);
|
|
ASSERT_MSG(addr.IsImmediate(), "patch addr non imm, inst {}",
|
|
fmt::ptr(addr.Inst()));
|
|
ir.SetPatch(IR::PatchGeneric((addr.U32() >> 2) + off_dw), data_component);
|
|
}
|
|
};
|
|
|
|
AttributeRegion region = GetAttributeRegionKind(&inst, info, runtime_info);
|
|
if (num_dwords == 1) {
|
|
SetOutput(addr, IR::U32{data}, region, 0);
|
|
} else {
|
|
for (auto i = 0; i < num_dwords; i++) {
|
|
SetOutput(addr, IR::U32{ir.CompositeExtract(data, i)}, region, i);
|
|
}
|
|
}
|
|
inst.Invalidate();
|
|
break;
|
|
}
|
|
|
|
case IR::Opcode::LoadSharedU32:
|
|
case IR::Opcode::LoadSharedU64: {
|
|
IR::IREmitter ir{*block, IR::Block::InstructionList::s_iterator_to(inst)};
|
|
const IR::U32 addr{inst.Arg(0)};
|
|
const AttributeRegion region = GetAttributeRegionKind(&inst, info, runtime_info);
|
|
const u32 num_dwords = opcode == IR::Opcode::LoadSharedU32 ? 1 : 2;
|
|
ASSERT_MSG(region == AttributeRegion::InputCP ||
|
|
region == AttributeRegion::OutputCP,
|
|
"Unhandled read of patchconst attribute in hull shader");
|
|
const bool is_tcs_output_read = region == AttributeRegion::OutputCP;
|
|
const u32 stride = is_tcs_output_read ? runtime_info.hs_info.hs_output_cp_stride
|
|
: runtime_info.hs_info.ls_stride;
|
|
IR::Value attr_read;
|
|
if (num_dwords == 1) {
|
|
attr_read = ir.BitCast<IR::U32>(
|
|
ReadTessControlPointAttribute(addr, stride, ir, 0, is_tcs_output_read));
|
|
} else {
|
|
boost::container::static_vector<IR::Value, 4> read_components;
|
|
for (auto i = 0; i < num_dwords; i++) {
|
|
const IR::F32 component =
|
|
ReadTessControlPointAttribute(addr, stride, ir, i, is_tcs_output_read);
|
|
read_components.push_back(ir.BitCast<IR::U32>(component));
|
|
}
|
|
attr_read = ir.PackUint2x32(ir.CompositeConstruct(read_components));
|
|
}
|
|
inst.ReplaceUsesWithAndRemove(attr_read);
|
|
break;
|
|
}
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (runtime_info.hs_info.IsPassthrough()) {
|
|
// Copy input attributes to output attributes, indexed by InvocationID
|
|
// Passthrough should imply that input and output patches have same number of vertices
|
|
IR::Block* entry_block = *program.blocks.begin();
|
|
auto it = std::ranges::find_if(entry_block->Instructions(), [](IR::Inst& inst) {
|
|
return inst.GetOpcode() == IR::Opcode::Prologue;
|
|
});
|
|
ASSERT(it != entry_block->end());
|
|
++it;
|
|
ASSERT(it != entry_block->end());
|
|
++it;
|
|
// Prologue
|
|
// SetExec #true
|
|
// <- insert here
|
|
// ...
|
|
IR::IREmitter ir{*entry_block, it};
|
|
|
|
u32 num_attributes = Common::AlignUp(runtime_info.hs_info.ls_stride, 16) >> 4;
|
|
const auto invocation_id = ir.GetAttributeU32(IR::Attribute::InvocationId);
|
|
for (u32 attr_no = 0; attr_no < num_attributes; attr_no++) {
|
|
for (u32 comp = 0; comp < 4; comp++) {
|
|
IR::F32 attr_read =
|
|
ir.GetTessGenericAttribute(invocation_id, ir.Imm32(attr_no), ir.Imm32(comp));
|
|
// InvocationId is implicit index for output control point writes
|
|
ir.SetTcsGenericAttribute(attr_read, ir.Imm32(attr_no), ir.Imm32(comp));
|
|
}
|
|
}
|
|
// We could wrap the rest of the program in an if stmt
|
|
// CopyInputAttrsToOutputs(); // psuedocode
|
|
// if (InvocationId == 0) {
|
|
// PatchConstFunction();
|
|
// }
|
|
// But as long as we treat invocation ID as 0 for all threads, shouldn't matter functionally
|
|
}
|
|
}
|
|
|
|
void DomainShaderTransform(const IR::Program& program, const RuntimeInfo& runtime_info) {
|
|
const Info& info = program.info;
|
|
|
|
for (IR::Block* block : program.blocks) {
|
|
for (IR::Inst& inst : block->Instructions()) {
|
|
IR::IREmitter ir{*block, IR::Block::InstructionList::s_iterator_to(inst)};
|
|
const auto opcode = inst.GetOpcode();
|
|
switch (inst.GetOpcode()) {
|
|
case IR::Opcode::LoadSharedU32:
|
|
case IR::Opcode::LoadSharedU64: {
|
|
const IR::U32 addr{inst.Arg(0)};
|
|
AttributeRegion region = GetAttributeRegionKind(&inst, info, runtime_info);
|
|
const u32 num_dwords = opcode == IR::Opcode::LoadSharedU32 ? 1 : 2;
|
|
const auto GetInput = [&](IR::U32 addr, u32 off_dw) -> IR::F32 {
|
|
if (region == AttributeRegion::OutputCP) {
|
|
return ReadTessControlPointAttribute(
|
|
addr, runtime_info.vs_info.hs_output_cp_stride, ir, off_dw, false);
|
|
} else {
|
|
ASSERT(region == AttributeRegion::PatchConst);
|
|
return ir.GetPatch(IR::PatchGeneric((addr.U32() >> 2) + off_dw));
|
|
}
|
|
};
|
|
IR::Value attr_read;
|
|
if (num_dwords == 1) {
|
|
attr_read = ir.BitCast<IR::U32>(GetInput(addr, 0));
|
|
} else {
|
|
boost::container::static_vector<IR::Value, 4> read_components;
|
|
for (auto i = 0; i < num_dwords; i++) {
|
|
const IR::F32 component = GetInput(addr, i);
|
|
read_components.push_back(ir.BitCast<IR::U32>(component));
|
|
}
|
|
attr_read = ir.PackUint2x32(ir.CompositeConstruct(read_components));
|
|
}
|
|
inst.ReplaceUsesWithAndRemove(attr_read);
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Run before either hull or domain transform
|
|
void TessellationPreprocess(IR::Program& program, RuntimeInfo& runtime_info) {
|
|
TessellationDataConstantBuffer tess_constants;
|
|
Shader::Info& info = program.info;
|
|
// Find the TessellationDataConstantBuffer V#
|
|
for (IR::Block* block : program.blocks) {
|
|
for (IR::Inst& inst : block->Instructions()) {
|
|
auto found_tess_consts_sharp = [&]() -> bool {
|
|
switch (inst.GetOpcode()) {
|
|
case IR::Opcode::LoadSharedU32:
|
|
case IR::Opcode::LoadSharedU64:
|
|
case IR::Opcode::WriteSharedU32:
|
|
case IR::Opcode::WriteSharedU64: {
|
|
IR::Value addr = inst.Arg(0);
|
|
auto read_const_buffer = IR::BreadthFirstSearch(
|
|
addr, [](IR::Inst* maybe_tess_const) -> std::optional<IR::Inst*> {
|
|
if (maybe_tess_const->GetOpcode() == IR::Opcode::ReadConstBuffer) {
|
|
return maybe_tess_const;
|
|
}
|
|
return std::nullopt;
|
|
});
|
|
if (read_const_buffer) {
|
|
auto sharp_location = FindTessConstantSharp(read_const_buffer.value());
|
|
if (sharp_location) {
|
|
if (info.tess_consts_dword_offset >= 0) {
|
|
// Its possible theres a readconstbuffer that contributes to an
|
|
// LDS address and isnt a TessConstant V# read. Could improve on
|
|
// this somehow
|
|
ASSERT_MSG(static_cast<s32>(sharp_location->dword_off) ==
|
|
info.tess_consts_dword_offset &&
|
|
sharp_location->ptr_base ==
|
|
info.tess_consts_ptr_base,
|
|
"TessConstants V# is ambiguous");
|
|
}
|
|
InitTessConstants(sharp_location->ptr_base,
|
|
static_cast<s32>(sharp_location->dword_off), info,
|
|
runtime_info, tess_constants);
|
|
return true;
|
|
}
|
|
UNREACHABLE_MSG("Failed to match tess constant sharp");
|
|
}
|
|
return false;
|
|
}
|
|
default:
|
|
return false;
|
|
}
|
|
}();
|
|
|
|
if (found_tess_consts_sharp) {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
ASSERT(info.tess_consts_dword_offset >= 0);
|
|
|
|
TessConstantUseWalker walker;
|
|
|
|
for (IR::Block* block : program.blocks) {
|
|
for (IR::Inst& inst : block->Instructions()) {
|
|
if (inst.GetOpcode() == IR::Opcode::ReadConstBuffer) {
|
|
auto sharp_location = FindTessConstantSharp(&inst);
|
|
if (sharp_location && sharp_location->ptr_base == info.tess_consts_ptr_base &&
|
|
sharp_location->dword_off == info.tess_consts_dword_offset) {
|
|
// The shader is reading from the TessConstants V#
|
|
IR::Value index = inst.Arg(1);
|
|
|
|
ASSERT_MSG(index.IsImmediate(),
|
|
"Tessellation constant read with dynamic index");
|
|
u32 off_dw = index.U32();
|
|
ASSERT(off_dw <=
|
|
static_cast<u32>(TessConstantAttribute::FirstEdgeTessFactorIndex));
|
|
|
|
auto tess_const_attr = static_cast<TessConstantAttribute>(off_dw);
|
|
switch (tess_const_attr) {
|
|
case TessConstantAttribute::LsStride:
|
|
// If not, we may need to make this runtime state for TES
|
|
ASSERT(info.l_stage == LogicalStage::TessellationControl);
|
|
inst.ReplaceUsesWithAndRemove(IR::Value(tess_constants.ls_stride));
|
|
break;
|
|
case TessConstantAttribute::HsCpStride:
|
|
inst.ReplaceUsesWithAndRemove(IR::Value(tess_constants.hs_cp_stride));
|
|
break;
|
|
case TessConstantAttribute::HsNumPatch:
|
|
case TessConstantAttribute::HsOutputBase:
|
|
case TessConstantAttribute::PatchConstBase:
|
|
walker.MarkTessAttributeUsers(&inst, tess_const_attr);
|
|
// We should be able to safely set these to 0 so that indexing happens only
|
|
// within the local patch in the recompiled Vulkan shader. This assumes
|
|
// these values only contribute to address calculations for in/out
|
|
// attributes in the original gcn shader.
|
|
// See the explanation for why we set V2 to 0 when emitting the prologue.
|
|
inst.ReplaceUsesWithAndRemove(IR::Value(0u));
|
|
break;
|
|
case Shader::TessConstantAttribute::PatchConstSize:
|
|
case Shader::TessConstantAttribute::PatchOutputSize:
|
|
case Shader::TessConstantAttribute::OffChipTessellationFactorThreshold:
|
|
case Shader::TessConstantAttribute::FirstEdgeTessFactorIndex:
|
|
// May need to replace PatchConstSize and PatchOutputSize with 0
|
|
break;
|
|
default:
|
|
UNREACHABLE_MSG("Read past end of TessConstantsBuffer");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// These pattern matching are neccessary for now unless we support dynamic indexing of
|
|
// PatchConst attributes and tess factors. PatchConst should be easy, turn those into a single
|
|
// vec4 array like in/out attrs. Not sure about tess factors.
|
|
if (info.l_stage == LogicalStage::TessellationControl) {
|
|
// Replace the BFEs on V1 (packed with patch id within VGT and output cp id)
|
|
for (IR::Block* block : program.blocks) {
|
|
for (auto it = block->Instructions().begin(); it != block->Instructions().end(); it++) {
|
|
IR::Inst& inst = *it;
|
|
if (M_BITFIELDUEXTRACT(
|
|
M_GETATTRIBUTEU32(MatchAttribute(IR::Attribute::PackedHullInvocationInfo),
|
|
MatchIgnore()),
|
|
MatchU32(0), MatchU32(8))
|
|
.Match(IR::Value{&inst})) {
|
|
IR::IREmitter emit(*block, it);
|
|
// This is the patch id within the VGT, not the actual PrimitiveId
|
|
// in the draw
|
|
IR::Value replacement(0u);
|
|
inst.ReplaceUsesWithAndRemove(replacement);
|
|
} else if (M_BITFIELDUEXTRACT(
|
|
M_GETATTRIBUTEU32(
|
|
MatchAttribute(IR::Attribute::PackedHullInvocationInfo),
|
|
MatchIgnore()),
|
|
MatchU32(8), MatchU32(5))
|
|
.Match(IR::Value{&inst})) {
|
|
IR::IREmitter ir(*block, it);
|
|
IR::Value replacement;
|
|
if (runtime_info.hs_info.IsPassthrough()) {
|
|
// Deal with annoying pattern in BB where InvocationID use makes no
|
|
// sense (in addr calculation for patchconst or tess factor write)
|
|
replacement = ir.Imm32(0);
|
|
} else {
|
|
replacement = ir.GetAttributeU32(IR::Attribute::InvocationId);
|
|
}
|
|
inst.ReplaceUsesWithAndRemove(replacement);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
ConstantPropagationPass(program.post_order_blocks);
|
|
}
|
|
|
|
} // namespace Shader::Optimization
|